Accurate estimates of soft error rates (SER's) in computer systems are desirable for the implementation of reliable systems. Soft errors are caused by single-event upsets (SEU's), which are random, isolated events that can be caused by passage of cosmic rays or transient ionizing particles, such as alpha particles. That is, ionizing particles can generate enough free charge to flip a structure or device to its opposite state. In an integrated circuit (IC) chip package, emission of trace amounts of radioactive impurities is one cause of SEU's. For wire-bonded structures, accelerated testing using a radioactive source of alpha particles is straightforward. In particular, a source of alpha particles with a known emission rate, such as, for example, a thorium foil, may be easily positioned adjacent to the wire-bonded chip with little energy loss as viewed from the source to the chip.
Unfortunately, however, for integrated circuits (IC's) that use, for example, solder bumps or balls, such as controlled collapsible chip connections (herein referred to as solder bumps), the chip-to-substrate gap is too small (e.g., on the order of 100 microns or less) to allow access by a hand-held radioactive source. Furthermore, the substrate blocks any access to the semiconductor device by a radioactive source, handheld or otherwise. Moreover, the range of alpha particles is substantially smaller than the thickness of the substrate, such that the alpha particles emitted from an external source cannot reach the semiconductor device. Typically, a low alpha emission underfill is inserted into the gap in order to stabilize the solder bond and act as a shield or block for any alpha particles that may emanate from the substrate or carrier.
Eliminating lead from the solder bumps reduces, but does not eliminate, the alpha radiation to the chip. Other sources of alpha particles may be, for example, trace amounts of thorium in chip materials that have been produced from mined ores. In addition, alpha particles from packaging materials, or solder bumps, add to, or compete with, neutron-induced soft errors caused by the liberation of charged particles when atmospheric neutrons strike silicon or other materials surrounding the chips. Disadvantageously, soft errors occur with greater frequency with advances in CMOS technology, for example; i.e., as dimensions get smaller, densities increase, and bias voltages become lower. Furthermore, while soft errors in caches and other static random access memory (SRAM) arrays can be detected and corrected with the aid of error correction codes (ECC's), for example, this is not the case for soft errors in logic circuits.
A current method for estimating soft error rates (SER's) is to add the soft error contributions from each circuit element. To this end, derating factors need to be estimated, and these are affected by, for example, SEU's in a portion of an IC that is not being used, or a node that is a logical off state. Unfortunately, therefore, these derating factors are difficult to estimate. Furthermore, relying on measurements from systems being tested in the field necessitates delays in acquisition of SER information until after a product is made.
Accordingly, it is desirable to provide a technique for packaging IC's to enable accelerated detection, in situ, of SER's due to transient particle emission.